The present invention relates, in general, to substrate bias control circuits and methods. More particularly, the present invention relates to the aforesaid circuits and methods which are of especial utility in controlling the application of supply and substrate voltages to CMOS devices utilizing separate voltage levels therefor.
Scaled CMOS devices, those having a channel length on the order of 1.25 microns, require a reduced power supply (V.sub.CC) for proper operation. That is, as channel lengths have decreased, a concomitantly reduced power supply voltage level is mandated in order to avoid excessive drain voltage reduction of the short channel device threshold voltage. However, such a reduced supply level (in the 3.0 volt range) prevents acceptance of more conventional 5.0 volt input logic swings when conventional CMOS input protection structures are used. It follows that with the 3.0 volt V.sub.CC supply connected to the N type substrate, as is conventional in CMOS technology, the use of a PN diode in the input protection circuitry would be precluded. Therefore, a novel technique for applying a 5.0 volt (V.sub.BB) substrate bias to the scaled CMOS circuit has been proposed which retains the PN diode of the input protection circuitry and still allows a 5.0 volt input logic swing to be applied thereto. A more detailed description of this technique is given in U.S. patent application Ser. No. 452,532 as filed on Dec. 23, 1982 by Charles S. Meyer and assigned to the assignee of the present invention. However, when using a 5.0 volt substrate bias voltage and a separate 3.0 volt supply voltage for these small geometry CMOS devices, it is necessary that the substrate voltage be applied before the supply voltage. Should the substrate not be biased before the supply voltage is applied, damage could result to the chip due to the forward biasing of the gate protection diode and the source to substrate junctions in the P channel devices. Typically, conventional CMOS structures have the substrate directly connected internally to the V.sub.CC supply to assure that substrate bias is applied whenever the device is powered up.
It is therefore an object of the present invention to provide an improved substrate bias control circuit and method.
It is further an object of the present invention to provide an improved substrate bias control circuit and method which allows separate circuit supply and substrate bias voltages to be applied or removed in either sequence without resultant chip damage.
It is still further an object of the present invention to provide an improved substrate bias control circuit and method which allows for chip operation on the circuit supply voltage only, in the absence of a substrate bias voltage, by connecting the substrate to the supply voltage until substrate voltage is applied.
It is still further an object of the present invention to provide an improved substrate bias control circuit and method which allows for isolation between sources of circuit supply and substrate bias voltage supply.
It is still further an object of the present invention to provide an improved substrate bias control circuit and method which is simply implemented requiring only nominal on-chip area.
It is still further an object of the present invention to provide an improved substrate bias control circuit and method which dissipates very little circuit power.